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-- Company: 
-- Engineer:
--
-- Create Date:   22:06:45 02/11/2011
-- Design Name:   
-- Module Name:   /home/cesar/cemisidfft_chip/cemisidfft_testbench.vhd
-- Project Name:  cemisidfft_chip
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: cemisidfft_chip
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY cemisidfft_testbench IS
END cemisidfft_testbench;
 
ARCHITECTURE behavior OF cemisidfft_testbench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT cemisidfft_chip
    PORT(
         CLK_i : IN  std_logic;
         RESET_i : IN  std_logic;
         LOAD_i : IN  std_logic;
         INIT_ADDRESS_i : IN  std_logic_vector(5 downto 0);
         C_o : OUT  std_logic;
         OVF_o : OUT  std_logic;
         N_o : OUT  std_logic;
         Z_o : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK_i : std_logic := '0';
   signal RESET_i : std_logic := '0';
   signal LOAD_i : std_logic := '0';
   signal INIT_ADDRESS_i : std_logic_vector(5 downto 0) := (others => '0');

 	--Outputs
   signal C_o : std_logic;
   signal OVF_o : std_logic;
   signal N_o : std_logic;
   signal Z_o : std_logic;

   -- Clock period definitions
   constant CLK_i_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: cemisidfft_chip PORT MAP (
          CLK_i => CLK_i,
          RESET_i => RESET_i,
          LOAD_i => LOAD_i,
          INIT_ADDRESS_i => INIT_ADDRESS_i,
          C_o => C_o,
          OVF_o => OVF_o,
          N_o => N_o,
          Z_o => Z_o
        );

   -- Clock process definitions
   CLK_i_process :process
   begin
		CLK_i <= '0';
		wait for CLK_i_period/2;
		CLK_i <= '1';
		wait for CLK_i_period/2;
   end process;
 

   -- Stimulus process
    stim_proc: process
    begin		
        -- hold reset state for 100 ns.
        wait for 100 ns;	

        wait for CLK_i_period*10;

        INIT_ADDRESS_i <= (others => '0');
        LOAD_i <= '0';
        RESET_i <= '1';

        wait for CLK_i_period*2;

	RESET_i <= '0';

        wait;
    end process;

END;
